Pontificia Universidad Católica de Chile Pontificia Universidad Católica de Chile
Herrera T., Núñez F. (2020)

Design and Prototyping of a Thread Border Router Based on a Non Network-co-Processor Architecture

Revista : IEEE Access
Volumen : 8
Páginas : 60613 - 60625
Tipo de publicación : ISI Ir a publicación


The IPv6-native home-area-network-oriented Thread protocol stack is currently attracting attention from both academic and commercial consumer electronics communities. In a Thread mesh deployment, as with any 6LoWPAN-based solution, a key element is the border router, since integration to the world-wide web depends exclusively on its performance. The typical architecture of a Thread border router involves a low-capable Thread-enabled device that acts as a slave of a more powerful host device owning a second networking interface, in what is known as a network-co-processor (NCP) architecture. To provide an alternative, this work focuses on the design and prototyping of a Thread border router using a non-NCP architecture. The challenges faced in implementing a non-NCP border router are detailed and a benchmark against a state-of-the-art NCP border router is presented. Results show that the non-NCP border router reduces the out-of-mesh latency by a factor of two. Immaturity of the IEEE 802.15.4 subsystem in the Linux kernel was evident during design and further work in such area is likely to improve dramatically the results obtained.