Pontificia Universidad Católica de Chile Pontificia Universidad Católica de Chile

Predictive Control Algorithm for Phase-Locked Loops

Revista : IEEE International Symposium on Circuits and Systems (ISCAS)
Tipo de publicación : Conferencia No DCC


Phase-locked loops (PLLs) exhibit a tradeoff between settling time and noise rejection, due to the fact that a low noise PLL requires a narrow bandwidth (BW) loop filter, which degrades settling time. However, the moments when fast settling or good noise rejection is required are clearly identified in a PLL, and this can be used to overcome this tradeoff. A recent technique – PLL gear shifting – exploits this fact by modifying the loop filter BW according to the PLL current objective. In this work, a similar solution based on predictive control techniques is presented. Through a very simple digital loop filter an optimal response is obtained, where a single parameter controls the bandwidth to improve either settling time or noise rejection.